Both U.S. Pat. No. 6,300,223 to Chang, et al. and United States Patent Application Publication 2006/0264035 to Nogami provide general descriptions of die seal ring structures and each proposes a different approach to reduce stress induced during the wafer dicing (cutting) process. U.S. Pat. No. 6,300,223 to Chang, et al. and United States Patent Application Publication 2006/0264035 are incorporated herein by reference.
Due to shrinking dimensions for the devices fabricated on an integrated circuit, fabrication processes are now utilizing low or ultra low K dielectric material. Utilization of such dielectric material may affect reliability due to its inferior mechanical properties (e.g., low modulus, low strength, poor adhesion) as compared to conventional dielectrics (e.g., silicon dioxide). In addition, technology reduction with a decrease in saw street width (in order to obtain extra space to accommodate more transistors in the integrated circuit) may cause an increased risk of crack propagation into the stack layer or at the pre-metal dielectric and silicon substrate interface. Further, with 3D Through-Silicon Via (TSV) assembly technology emerging in the near future, dicing of stacked wafers (i.e., especially for the wafer backside), can potentially trigger cracking at the pre-metal dielectric and silicon substrate interface.
Now turning to FIG. 1, there is shown a cross-sectional view of a typical die seal ring structure 110 fabricated around the perimeter of the active area 120 (i.e., the integrated circuit) of a die 100 on a wafer. The die ring seal 110 includes a crack stop structure (CS) 130 designed to prevent crack propagation and a moisture oxidation barrier (MOB) 140 to reduce moisture ingression into the active die area during the dice process, package and assembly process, and environmental stress conditioning. As illustrated in FIG. 1, small buffer areas separate the CS 130 from a saw street region 150, the CS 130 from the MOB 140, and the MOB 140 from the active area 120. During wafer dicing, a substantial amount of stress (energy) is generated from the cutting action along the saw street. This stress is usually transferred laterally to the die seal ring region and may cause cracking in weak materials or material interfaces, and cracking may propagate into the active area. Cracking within the active area usually renders the integrated circuit defective.
In U.S. Pat. No. 6,300,223, a substrate trench (unfilled) is fabricated in a buffer space (i.e., the saw street region) adjacent a scribe line to reduce lateral stress during wafer cutting. This approach does not appear to address the crack propagation problem at the pre-metal dielectric and silicon substrate interface. In US Patent Application Publication No. 2006/0264035, a crack stop trench is formed and filled with material having high crack resistance. One problem with the fabrication method disclosed therein is the difficulty in etching the crack stop trench through four layers of material (two metal, one inter-level dielectric, and one dielectric). Moreover, the resulting interface between the crack stop trench fill material and the silicon substrate may not be strong enough to resist crack propagating at the interface.
Current crack stop structures, such as the CS 130 in FIG. 1, might adequately prevent crack propagation between different metal layers and dielectric material layers in the stack layer, but may not protect against cracking in a weak mechanical interface between the pre-metal dielectric layer (CA) and the silicon (semiconductor) substrate 160.
Therefore, there is a need for an improved crack stop structure (and method of fabricating) in the die seal ring surrounding the active area of a die on a wafer.